1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a semiconductor memory device having a redundant circuit.
2. Description of the Background Art
Recently, as the storage capacity of a semiconductor memory device is increased, the number of memory cells provided in a semiconductor memory of one chip is remarkably increased. With such increase in the number of memory cells, the ratio of products with no defects in their memory cell array portions to all the semiconductor memory chips manufactured, (so-called "yield") is notably lowered.
Therefore, most of recent semiconductor memory devices include, in addition to memory cell arrays originally to be used (hereinafter referred to as normal memory cell arrays), memory cell arrays to be used in place of the normal memory cell arrays in case defects are generated therein due to causes arising in manufacture (hereinafter referred to as spare memory cell arrays).
Actually, one of memory cell rows or memory cell columns in a spare memory cell array is used in place of a memory cell row or a memory cell column to which a defective memory cell in a normal memory cell array belongs.
FIG. 10 is a schematic block diagram showing the whole configuration of a conventional semiconductor memory device having spare memory cell arrays. FIG. 10 mainly shows circuitry portions serving for controlling operations of normal memory cell arrays and spare memory cell arrays as peripheral circuitry of those memory cell arrays.
Now, referring to FIG. 10, description will be given of the configuration of the conventional semiconductor memory device, mainly of circuit operations performed in the semiconductor memory device for the purpose of using normal memory cell arrays and spare memory cell arrays appropriately.
Each of a plurality of normal memory cell arrays 31-1 to 31-n is provided with two types of spare memory cell arrays (32-1 to 32-n, 33-1 to 33-n).
FIG. 11 is a diagram showing the configuration of arbitrary one of normal memory cell arrays 31-1 to 31-n and the spare memory cell arrays added thereto.
Referring to FIG. 11, each of normal memory cell arrays 31-1 to 31-n includes memory cells MC arranged in a plurality of rows and a plurality of columns, word lines WL provided corresponding, respectively, to the memory cell rows, and bit lines (or bit line pairs) BL provided corresponding, respectively, to the memory cell columns. Each of the word lines WL is connected to all the memory cells MC included in a corresponding one of the memory cell rows, and each of the bit lines (or bit line pairs) BL is connected to all the memory cells MC included in a corresponding one of the memory cell columns.
Each of spare memory cell arrays 32-1 to 32-n includes the plurality of word lines WL, in common with a corresponding one of normal memory cell arrays 31-1 to 31-n, and further includes at least one (or one pair of) spare bit line (or spare bit lines) SBL, independently of the corresponding one of normal memory cell arrays 31-1 to 31-n. A spare memory cell column including spare memory cells SMC of the same number as the number of the word lines WL is provided corresponding to each spare bit line (or spare bit line pair) SBL. Each of the spare memory cells SMC is connected to a corresponding one spare bit line (or bit line pair) SBL and a corresponding one of the word lines WL.
Each of spare memory cell arrays 33-1 to 33-n includes a plurality of bit lines (or bit line pairs) BL, in common with a corresponding one of normal memory cell arrays 31-1 to 31-n, and further includes at least one spare word line SWL, independently of the corresponding one of normal memory cell arrays 31-1 to 31-n. A spare memory cell row including spare memory cells SMC of the same number as the number of the bit lines (or bit line pairs) BL is provided corresponding to each spare word line SWL. Each of the spare memory cells SMC is connected to a corresponding one of the bit lines (or bit line pairs) BL and a corresponding one spare word line SWL.
As shown in FIGS. 10 and 11, normal row decoders 25-1 to 25-n and normal column decoders 42-1 to 42-n are provided to respective normal memory cell arrays 31-1 to 31-n, and spare row decoders 24-1 to 24-n and spare column decoders 41-1 to 41-n are provided to spare memory cell arrays 33-1 to 33-n and spare memory cell arrays 32-1 to 32-n, respectively.
Each of normal row decoders 25-1 to 25-n selectively activates one of the word lines WL in a corresponding one of normal memory cell arrays 31-1 to 31-n. This makes it possible to transfer a data signal between each of the memory cells MC connected to the one word line WL and a corresponding bit line BL.
Each of normal column decoders 42-1 to 42-n makes it possible to withdraw a signal from one of the bit lines (or bit line pairs) BL in a corresponding one of normal memory cell arrays 31-1 to 31-n and to apply an external data signal to the one bit line (or bit line pair) BL. Accordingly, it becomes possible to write and read data into/from one memory cell MC connected to the activated word line WL out of the memory cells MC connected to the one bit line (or bit line pair) BL.
Each of spare row decoders 24-1 to 24-n selectively activates one of the spare word lines SWL in a corresponding one of spare memory cell arrays 33-1 to 33-n. This makes it possible to transfer a data signal between each of the spare memory cells SMC connected to the one spare word line SWL and a corresponding bit line BL.
Each of spare column decoders 41-1 to 41-n makes it possible to withdraw a data signal from one of the spare bit lines (or bit line pairs) SBL in a corresponding one of spare memory cell arrays 32-1 to 32-n and to supply an external data signal to the one bit line (or bit line pair) SBL.
However, each of normal row decoders 25-1 to 25-n and a corresponding one of spare row decoders 24-1 to 24-n do not operate simultaneously, and they are controlled so that only one of them operates. Similarly, each of normal column decoders 42-1 to 42-n and a corresponding one of spare column decoders 41-1 to 41-n do not operate simultaneously, and they are controlled so that only one of them operates.
For example, in a case where there are two or more defective memory cells in the same row or any one of the word lines WL is defective in an arbitrary one of normal memory cell arrays 31-1 to 31-n, it is necessary that one of the spare memory cell rows in one of spare memory cell arrays 33-1 to 33-n provided corresponding to that normal memory cell array is used in place of the memory cell row including the defective memory cells or the memory cell row provided corresponding to the defective word line WL.
Therefore, in such a case, out of the normal row decoder and the spare row decoder corresponding to that normal memory cell array including the defective memory cell row, the spare row decoder is activated in response to an external address signal indicating the defective memory cell row.
At the same time, in one of spare memory cell arrays 32-1 to 32-n corresponding to that normal memory cell array, it becomes possible to transfer a data signal between each of the spare memory cells SMC connected to one of the word lines WL which is activated by operation of a corresponding one of normal row decoders 25-1 to 25-n and a corresponding one of the spare bit lines (or bit line pairs) SBL. Therefore, it becomes possible to write and read data into/from one of the spare memory cell rows in one of the spare memory cell arrays 33-1 to 33-n provided corresponding to the normal memory cell array instead of writing and reading data into/from the defective memory cell row. Specifically, the defective memory cell row is replaced by a non-defective spare memory cell row.
Similarly, in a case where there are two or more defective memory cells MC in the same column or where any one of the bit lines BL is defective in an arbitrary one of normal memory cell arrays 31-1 to 31-n, it is necessary that any one of the spare memory cell columns in one of spare memory cell arrays 32-1 to 32-n provided corresponding to that normal memory cell array is used in place of the memory cell column including the defective memory cell MC or the memory cell column provided corresponding to the defective bit line BL.
Therefore, in such a case, out of one of normal column decoders 42-1 to 42-n and one of spare column decoders 41-1 to 41-n corresponding to the normal memory cell array including that memory cell column, the spare column decoder is activated in response to an external address signal indicating the defective memory cell column.
At the same time, in one of spare memory cell arrays 33-1 to 33-n corresponding to that normal memory cell array, operation of a corresponding one of normal column decoders 42-1 to 42-n makes it possible to write and read data into/from one spare memory cell SMC connected to the activated spare word line SWL out of the spare memory cells SMC connected to one bit line (or bit line pair) BL. Therefore, it becomes possible to write and read data into/from a non-defective spare memory cell column instead of writing and reading data into/from the defective memory cell column. Specifically, the defective memory cell column is replaced by the non-defective spare memory cell column.
Thus, a defective memory cell row and a defective memory cell column in each of normal memory cell arrays 31-1 to 31-n are replaced, respectively, by a spare memory cell row in one of the first spare memory cell arrays 33-1 to 33-n provided corresponding to the normal memory cell array and a spare memory cell column in one of the second spare memory cell arrays 32-1 to 32-n provided corresponding to the normal memory cell array.
In order to perform this replacement, as shown in FIG. 10, spare row decoder activating circuits 21-1 to 21-n are provided corresponding, respectively, to spare row decoders 24-1 to 24-n, and spare column decoder activating circuits 44-1 to 44-n are provided corresponding, respectively, to spare column decoders 41-1 to 41-n.
Each of spare row decoder activating circuits 21-1 to 21-n provides a control signal (SRE1-SREn) for activating either a corresponding one of spare row decoders 24-1 to 24-n or one of normal row decoders 25-1 to 25-n corresponding to that spare row decoder and for deactivating the other in response to an output signal of a row address buffer 20.
Similarly, each of spare column decoder activating circuits 44-1 to 44-n provides a control signal (SCE1-SCEn) for activating either a corresponding one of spare column decoders 41-1 to 41-n or one of normal column decoders 42-1 to 42-n corresponding to that spare column decoder and for deactivating the other in response to an output of a column address buffer 40.
Row address buffer 20 buffers a row address signal out of external address signals applied through external terminals 23 which indicates in which row in normal memory cell arrays 31-1 to 31-n data should be written or read into/from a memory cell arranged therein and supplies it to normal row decoders 25-1 to 25-n, spare row decoders 24-1 to 24-n, and spare row decoder activating circuits 21-1 to 21-n.
Column address buffer 40 buffers a column address signal out of the above external address signals which indicates in which column in normal memory cell arrays 31-1 to 31-n data should be written or read into/from a memory cell arranged therein and supplies it to normal column decoders 42-1 to 42-n, spare column decoders 41-1 to 41-n, and spare column decoder activating circuits 44-1 to 44-n.
In a case where the column address signal from column address buffer 40 indicates a defective memory cell column in one of normal memory cell arrays 31-1 to 31-n, a corresponding one of spare column decoder activating circuits 44-1 to 44-n activates a corresponding one of spare column decoders 41-1 to 41-n while deactivating a corresponding one of normal column decoders 42-1 to 42-n. In the other case where the column address signal from column address buffer 40 indicates a non-defective memory cell column, each of spare column decoder activating circuits 44-1 to 44-n deactivates a corresponding one of spare column decoders 41-1 to 41-n and activates a corresponding one of normal column decoders 42-1 to 42-n.
Similarly, in a case where the row address signal from row address buffer 20 indicates a defective memory cell row in one of normal memory cell arrays 31-1 to 31-n, a corresponding one of spare row decoder activating circuits 21-1 to 21-n activates a corresponding one of spare row decoders 24-1 to 24-n while deactivating a corresponding one of normal row decoders 25-1 to 25-n. In the other case where the row address signal from row address buffer 20 indicates a non-defective memory cell row, each of spare row decoder activating circuits 21-1 to 21-n deactivates corresponding one of spare row decoders 24-1 to 24-n while activating a corresponding one of normal row decoders 25-1 to 25-n.
Specifically, each of spare column decoder activating circuits 44-1 to 44-n includes a plurality of fuses. Each of spare column decoder activating circuits 44-1 to 44-n has any of the plurality of fuses selectively cut in advance so that its output signal (SCE1-SCEn) activates a corresponding one of spare column decoders 41-1 to 41-n when a column address signal indicating a defective memory cell column in a corresponding one of normal memory cell arrays 31-1 to 31-n is applied thereto from column address buffer 40.
Similarly, each of spare row decoder activating circuits 21-1 to 21-n includes a plurality of fuses. Each of spare row decoder activating circuits 21-1 to 21-n has any of the plurality of fuses selectively cut in advance so that its output signal (SRE1-SREn) is a one capable of activating a corresponding one of spare row decoders 24-1 to 24-n only when a row address signal indicating a defective memory cell row in a corresponding one of normal memory cell arrays 31-1 to 31-n is applied thereto from row address buffer 20.
Each of spare column decoders 41-1 to 41-n makes it possible to supply an external data signal to spare bit line SBL corresponding to one of the memory cell columns in a corresponding one of spare memory cell arrays 32-1 to 32-n and to withdraw a data signal from the spare bit line SBL, in response to a column address signal from column address buffer 40, in a period in which the spare column decoder is activated by a corresponding one of spare column decoder activating circuits 44-1 to 44-n.
Similarly, each of spare row decoders 24-1 to 24-n activates one of the spare word lines SWL provided corresponding to one of the spare memory cell rows in a corresponding one of spare memory cell arrays 33-1 to 33-n, in response to a row address signal from row address buffer 20, in a period in which the spare row decoder is activated by a corresponding one of spare row decoder activating circuits 21-1 to 21-n.
As described above, in order to make it possible to actually use so-called redundant circuits such as spare memory cell arrays 32-1 to 32-n, 33-1 to 33-n, spare column decoders 41-1 to 41-n, and spare row decoders 24-1 to 24-n which are to be used replacing normal memory cell arrays 31-1 to 31-n, normal column decoders 42-1 to 42-n, and normal row decoders 25-1 to 25-n, respectively, circuitry (spare column decoder activating circuits 44-1 to 44-n and spare row decoder activating circuits 21-1 to 21-n) provided for activating those redundant circuits under particular conditions are set to a particular state by cutting fuses during manufacture, for example.
Now, whether such redundant circuits are used or not is important information in carrying out a failure analysis in a semiconductor memory device after manufacture. Therefore, a semiconductor memory device having a redundant circuit is generally provided with a redundancy detecting circuit 22 in order to know whether the redundant circuits are used or not from the semiconductor memory device after manufacture.
A redundancy detecting circuit 22 is provided in the vicinity of any of external terminals 23 and supplies a signal indicating whether the redundancy circuits are used or not to that external terminal in the vicinity.
FIG. 12 is a schematic diagram showing a configuration of a conventional redundancy detecting circuit 22. The configuration and operation of conventional redundancy detecting circuit 22 will be described in the following with reference to FIG. 12.
A conventional redundant circuit includes an N-channel MOS transistor 2 provided between a predetermined external terminal 23 and ground GND and a serial connection circuit of a fuse 4 and an N-channel MOS transistor 3 connected in parallel with transistor 2. Gates of transistors 2 and 3 are grounded.
External terminal 23 is originally provided for transmitting a signal between a circuit part other than redundancy detecting circuit 22 and the outside and externally receives a predetermined negative voltage for operating redundancy detecting circuit 22 only when whether the redundancy circuits are used or not is tested.
In a case where any of the redundant circuits is used, i.e. in a case where any of the fuses in spare column decoder activating circuits 44-1 to 44-n and spare row decoder activating circuits 21-1 to 21-n is cut in advance in FIG. 11, fuse 4 in the redundancy detecting circuit is also cut.
First, an operation of redundant circuit 22 in a case where fuse 4 is not cut will be described.
If a negative voltage is applied to external terminal 23 with its absolute value V.sub.F gradually increased, current starts to flow in interconnection A, which connects external terminal 23 with transistor 2 and fuse 4, at the time when the absolute value V.sub.F becomes larger than respective threshold voltages Vth of transistors 2 and 3. Thereafter, the current flowing in the interconnection A is increased according to increase in the absolute value V.sub.F.
FIG. 13 is a graph showing the relation between the absolute value V.sub.F of the negative voltage applied to external terminal 23 and the magnitude of the current flowing in the interconnection A. In FIG. 13, the absolute value V.sub.F is indicated on the abscissa, and the magnitude I.sub.F of the current flowing in the interconnection A is indicated on the ordinate.
Referring to FIGS. 12 and 13, transistors 2 and 3 are both in OFF state so that current does not flow between external terminal 23 and ground GND until the absolute value V.sub.F of the negative voltage applied to external terminal 23 reaches respective threshold voltages Vth of transistors 2 and 3. However, if the absolute value V.sub.F exceeds the respective threshold voltages Vth of transistors 2 and 3, transistors 2 and 3 are both brought to ON state, so that current of a magnitude corresponding to the sum of the current between the source and the drain of transistor 2 and the current between the source and the drain of transistor 3 flows in the interconnection A in the direction of from ground GND toward external terminal 23. If the absolute value V.sub.F of the potential of external terminal 23 is increased, the potential between the gate and the source of each of transistors 2 and 3 is increased, so that the current flowing in the interconnection A is increased in proportion to the absolute value V.sub.F as shown by line 1 in FIG. 13.
Now, an operation of redundancy detecting circuit 22 in a case where fuse 4 is cut will be described.
Since fuse 4 is cut, no current flows from ground GND through fuse 4 and transistor 3 to the interconnection A regardless of the polarity and the absolute value of the potential of external terminal 23. Accordingly, if a negative voltage is applied to external terminal 23 with the absolute value V.sub.F of the voltage gradually increased, transistor 2 is in OFF state so that no current flows in the interconnection A until the absolute value V.sub.F reaches the threshold voltage Vth of transistor 2. However, if the absolute value V.sub.F reaches the threshold voltage Vth of transistor 2, transistor 2 is brought to ON state, so that current of a magnitude corresponding to the current between the source and drain of transistor 2 flows in the interconnection A in a direction of from ground GND toward external terminal 23. If the absolute value V.sub.F of the potential of external terminal 23 is increased in the range of the threshold voltage Vth of transistor 2 or more, the magnitude of the current flowing in the interconnection A is increased in proportion to the absolute value V.sub.F as shown by line 2 in FIG. 3.
As described above, the current flowing in the interconnection A in a case where a negative voltage having an absolute value Vin larger than the respective threshold value voltages Vth of transistors 2 and 3 is applied to external terminal 23 differs depending on whether fuse 4 is cut or not. Specifically, in a case where fuse 4 is cut, current I.sub.1 smaller than current I.sub.0 flowing in the interconnection A in a case where fuse 4 is not cut is detected from external terminal 23.
Therefore, in a case where whether the redundant circuits are used or not is tested in the semiconductor memory device after manufacture, a negative voltage having a predetermined absolute value Vin larger than the respective threshold voltages Vth of transistors 2 and 3 is applied to external terminal 23 connected to redundancy detecting circuit 22, and then the magnitude of the current flowing in external terminal 23 is detected. If the detected magnitude of current is smaller than a predetermined reference value, fuse 4 is considered to be cut, so that it is possible to determine that any of the redundant circuits is used in the semiconductor memory device. Conversely, if the detected magnitude of the current is larger than the predetermined reference value, fuse 4 is considered to be not cut, so that it is possible to determine that the redundant circuits are not used in the semiconductor memory device.
The reference value is set, for example, to the magnitude I.sub.1 of the current flowing in external terminal 23, which is measured by applying a negative voltage having an absolute value Vin to an external terminal 23 of another semiconductor memory device in which a fuse 4 is not cut.
The reference value is set, for example, to the magnitude of the current flowing between a reference circuit of the same structure as that of redundancy detecting circuit 22, which is provided corresponding to an external terminal other than external terminal 23 connected to redundancy detecting circuit 22, and that external terminal other than external terminal 23 in the semiconductor memory device having redundancy detecting circuit 22.
Specifically, the fuse included in the reference circuit is not cut regardless of whether the redundant circuits are used or not. A negative voltage having an absolute value Vin is applied to the external terminal connected to the reference circuit, and the magnitude of the current flowing in the external terminal is measured. The measured magnitude of the current is used as the above-described reference value.
As described above, the conventional semiconductor memory device having the redundant circuits has a redundancy detecting circuit so that it can test whether the redundant circuits are used or not after completion of the semiconductor memory device as a product. The redundancy detecting circuit includes a fuse which is selectively cut during manufacture according to whether the redundant circuits are used or not.
Whether the redundant circuits are used or not is set by selectively cutting a fuse provided in circuits other than the redundancy detecting circuit.
For example, referring to FIG. 10, whether spare memory cell arrays 32-1 to 32-n and 33-1 to 33-n are used or not is determined depending on whether the fuses in spare column decoder activating circuits 44-1 to 44-n and spare row decoders 24-1 to 24-n are cut during manufacture.
Accordingly, a manufacturing process of the conventional semiconductor memory device having the redundant circuits should include the troublesome step of cutting the fuse in the redundancy detecting circuit in addition to the step of cutting the fuse for determining whether the redundant circuits are used or not.
Furthermore, in the redundancy detecting circuit of the semiconductor memory device completed as a product, the state of the fuses (whether they are cut or not) has been already determined. Therefore, the reference value to be compared with the magnitude of the current measured by applying a predetermined negative voltage to the external terminal connected to the redundancy detecting circuit in order to determine whether the redundant circuits are used or not is not a value obtained by directly measuring the magnitude of the current flowing in the external terminal connected to the redundancy detecting circuit when the fuse in the redundancy detecting circuit is not cut.
Specifically, as described above, a value measured by operating another circuit connected to another external terminal such as a redundancy detecting circuit in another semiconductor memory device in which a fuse is not cut, a reference circuit provided connected to another external terminal in the same semiconductor memory device which has the same structure as that of the redundancy detecting circuit and in which a fuse is not cut, or the like is used.
However, the input impedances of external terminals, capacities of wiring, or the like do not correspond correctly even among circuits having the same structure, so that the value of the current measured by operating such another circuit does not correspond to the magnitude of the current which flows in the external terminal connected to the redundancy detecting circuit to be actually used for determining whether the redundant circuits are used or not when the fuse in the redundancy detecting circuit is not cut.
Therefore, according to the conventional redundancy detecting circuit, the reference value for determining whether the redundant circuits are used or not is incorrect, so that it is not always possible to correctly determine whether the redundant circuits are used or not.